For the realization of a fast, successive-approximation A/D converter in MOS technology, conventional voltage driven R-2R techniques are cumbersome since diffused resistors of proper sheet resistance are not available in the standard single-channel technology. A complex thin-film process must be used. Furthermore, these approaches require careful control of the "ON" resistance ratios in the MOS switches over a wide range of values.
In contrast to its utilization as a current switch, the MOS device, used as a charge switch, has inherently zero offset voltage and as an amplifier, has very high input resistance. In addition, capacitors are easily fabricated in metal gate technology. Therefore, one is lead to use capacitors rather than resistors as the precision components, and to use charge rather than current as the working medium. This technique, referred to as charge-redistribution, has been used in some discrete A/D converters for many years. However, these converters have required high-performance operational amplifiers which are difficult to realize in single-channel MOS technology.
A charge redistribution A/D conversion technique using binary weighted capacitors is illustrated with a 5-bit version of the converter shown in FIG. 1. It consists of a comparator 20, an array of binary weighted capacitors 22, plus one additional capacitor of weight corresponding to the least significant bit (LSB) 24, and switches 30, 34 which connect the plates to certain voltages. A conversion is accomplished by a sequence of three operations. In the first, the "sample mode" shown in FIG. 1, the top plate 26 is connected to a reset potential Vr, and the bottom plates 28 are connected to the input voltage, Vin. This results in a stored charge on the top plate 26 which is proportional to the difference between the input voltage, Vin and the reset potential, Vr. In the "hold mode" of FIG. 2, the top switch 30 is then opened, and the bottom plates 28 are connected to ground through switches 34. Since the charge on the top plate is conserved, its potential goes to (Vr-Vin). The "redistribution mode", shown in FIG. 3, consists of switching the bottom plate voltage of one capacitor at a time from ground to Vref, beginning with the most significant bit (MSB) i.e. the largest capacitor. The switching tests the value of the most significant bit (MSB). The equivalent circuit is now actually a voltage divider between two equal capacitances, due to the sequential binary weighting of the capacitances in the array. The voltage Vx, which was equal to (Vr-Vin) previously, is now increased by 1/2 the reference as a result of this operation. EQU Vx=Vr-Vin+Vref/2
Sensing the sign of Vx, the comparator output is a logic `1` if Vx&lt;0 and is a `0` if Vx&gt;0. This is analogous to the interpretation that EQU if Vx&lt;0 then (Vr- Vin)&gt; Vref/2;
hence the MSB=1; but EQU if Vx&gt;0 then (Vr-Vin)&lt;Vref/2;
therefore the MSB=0. The output of the comparator is, therefore, the value of the binary bit being tested. Switch S1 is returned to ground only if the MSB b4 is a zero. In a similar manner, the next MSB is determined by raising the bottom plate of the next largest capacitor to Vref and checking the polarity of the resulting value of Vx. In this case, however, the voltage division property of the array causes Vref/4 to be added to Vx: EQU Vx=Vr-Vin+b4(Vref/2)+b2(Vref/4).
Conversion proceeds in this manner until all the bits have been determined. A final configuration is illustrated in FIG. 4 for the digital output 01001. The total original charge on the top plates has been redistributed in a binary fashion. N redistributions are required for a conversion of N bits.